Design Verification (DV)
Company: L&T Technology Services Limited
Posted on: June 23, 2022
- The candidates should be having 8 + Years of VLSI Industry
experience in the Front end Verification using SV-UVM/OVM
- The role requires the following attributes in the candidate:
Hands-on verification experience and proficiency using System
Verilog and OVM/UVM2
- Interact closely with the architecture and design teams,
influencing product definition, implementation and validation.
Create, define and develop system validation environment and test
suites.- Responsible for the development of methodologies,
execution of validation test plans, test sequences and directed
- Proven track record in ASIC verification from environment
development to tests development
- Experience in development and deployment of verification
strategies and methodologies across teams and organizations
- Experience with implementation of modern verification
environments that include use of constrained-random stimulus and
use of functional coverage.
- Experience with SRAM,DRAMs, Clk-power architectures, AON, Multi
clock domains ets is a Plus.
- He should be able to Manage and Co-ordinate with the Off-shore
Keywords: L&T Technology Services Limited, Austin , Design Verification (DV), Other , Austin, Texas
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