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Functional Verification engineer-SAN

Company: SGS Consulting
Location: Austin
Posted on: September 13, 2019

Job Description:

Looking for a Functional verification engineer for the Unified Memory Controller(UMC) IP.
As a functional verification team member, you would:
--- Provide technical expertise for developing the functional verification strategy of AMD's next generation of Dram Controller (also known as UMC).

--- Maintain and enhance existing verification infrastructure.
--- Develop new test plans, functional coverage points, and test bench components like test-cases, monitors, scoreboards, sequencers, and sequences.
AMD uses IP-XACT methodology. UMC integrates the ddr phy into our IP and also integrates the UMC IP into each Client and Server SOC.

Daily activities include:

--- Looking at the RTL to find functional bugs,
--- Working with the RTL team to fix the bugs,
--- Reading the DRAM Controller MAS(Micro-architectural Spec) and Jedec Guidelines
--- Developing test plans, functional coverage points, monitors, scoreboards, sequencers, and sequences, which utilize scripts, System Verilog, UVM, DFT, and methodologies to increase the rate with which bugs are found and resolved.

The role generally entails a mixture of:
1. Ownership of a piece of our test bench,
2. Planning & execution of feature additions and
3. Next dram feature enablement using coverage
4. Bug fixes
5. debug of regression signatures.
--- MS or BS and 5+ yrs of Functional Verification experience
--- Requires strong Object Oriented programming and debug skills.
--- Requires exposure and experienc in Verilog and System Verilog(or some Object Oriented Programming like C++)
--- Requires exposure to scripting likePerl, and logic simulation;
--- Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.
--- Demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage is a plus.
--- Experience with OVM or UVM is a plus.

--- Experience with memory controllers, memory models(ddr4, ddr5, lpddr4, lpddr5 or hbm), Jedec and/or ddr phys is a plus.

Keywords: SGS Consulting, Austin , Functional Verification engineer-SAN, Engineering , Austin, Texas

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