Senior Digital Design Verification Engineer

Company: Silicon Laboratories Inc.
Location: Austin
Posted on: November 26, 2022

Job Description:

We are -Silicon Labs.---We are a leader in secure, intelligent wireless technology for a more connected world.---Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow -economies -and improve lives.--- -Digital IC Design Team at Silicon LabsThe Digital team is a state-of-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, -verification -and implementation of the Wireless MCU SoCs is the responsibility of the Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, machine learning, advanced security, state of the art power management, and best in class radios to support a wide range of wireless IoT applications and standards. - The Digital team has an immediate need for experienced verification engineers!Responsibilities

• Block and IP Verification
  • Block level verification to validate block performance and adherence to requirements
  • Generate and execute verification plan based on specifications
  • Architect and implement testbenches using UVM-based methods
  • Architect and implement Verification Components using UVM-based methods
  • Coverage definition, implementation, and analysis
  • Architect and implement Formal Verification
  • Verification of mixed-signal IP integration, including real-number modeling
  • SoC Integration and Verification
    • Define, test and debug use cases for the SoC using C code or UVM methods
    • Verify and debug low-power design
    • Debug SDF Back Annotated Gate Simulations
    • Flows and Methodology
      • Identify and develop verification flows and methodologies to enhance IP, SoC, Mixed Signal or Formal VerificationRequirements
        • 5+ years of experience
        • Industry experience developing testbenches and verification components with -SystemVerilog -and UVM -is required
        • Knowledge of scripting/language (Python, PERL, shell, TCL)
        • Design/Verification skills
          • Software/Firmware coding (C)
          • SystemVerilog Assertion and coverage analysisBenefits
            • Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental & vision plans.
            • Highly competitive salary.
            • 401k plan with match and Roth plan option.
            • Equity rewards (RSUs).
            • Employee Stock Purchase Plan (ESPP).
            • Life/AD&D and disability coverage.
            • Flexible spending accounts.
            • Adoption assistance.
            • Back-Up childcare.
            • Additional benefit options (Commuter benefits, Legal benefits, Pet insurance).
            • Flexible Vacation Plan.
            • 3 paid volunteer days per year.
            • Charitable contribution match.
            • Tuition reimbursement.
            • Free downtown parking.
            • Onsite gym.
            • Monthly wellness offerings.
            • Free snacks.
            • Monthly company updates with our CEO. -We are an equal opportunity employer and value diversity at our company. We do not discriminate -on the basis of -race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Keywords: Silicon Laboratories Inc., Austin , Senior Digital Design Verification Engineer, Engineering , Austin, Texas