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Design Verification Engineer

Company: ACS Solutions
Location: Austin
Posted on: November 25, 2022

Job Description:

Job Description:

Very strong DV engineer capable of working independently.
Must be able to build UVM agents, monitors, scoreboards from scratch.
Prior experience designing and implementing a verification environment for a complex RTL design (e.g. DMA controller, memory controller, CPU subsystem etc).
Domain expertise in one or more of the following areas (AXI/AHB, PCIe, DDR, knowledge of ARM Cortex, Synopsys ARC, Cadence Tensilica, RISC-V embedded controllers etc)
Prior experience participating in the full life cycle of ASIC projects (architecture through silicon to production)
Prior experience setting up and debugging gate level simulations with SDF annotated timing.
Good communication skills, open and collaborative working style, team player


Keywords: ACS Solutions, Austin , Design Verification Engineer, Engineering , Austin, Texas

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