R-10038434 RTL Design Engineer
Company: NXP Semiconductors
Posted on: August 7, 2022
THIS POSITION IS LOCATED IN AUSTIN, TX. HYBRID WORK SCHEDULE AND
LOTS OF FLEXIBILITY. UNLIMITED PAID TIME OFF. PAID MATERNITY AND
PATERNITY LEAVE. RELOCATION AND VISA SPONSORSHIP AVAILABLE TO THOSE
ALREADY IN THE US.
Business Unit DescriptionMCU/MPU Engineering Digital IP team
defines and develops components for a wide range of products,
including automotive microprocessors, application processors,
microcontrollers, and networking. The Austin Digital IP team
develops components for DDR, Ethernet, high-speed serial links,
cores, caches, and interconnect.
- Review IP architecture specifications, features and programming
model, microarchitecture and interface specifications.
- Plan IP documentation and design, including providing schedule
- Design IP meeting requirements for quality and performance,
using Verilog and System Verilog RTL, and vendor and internal
- Collaborate with verification team to develop test plans and
complete verification execution to 100% coverage, and as per NXP
standard quality and maturity standards.
- Deliver completed IP, including RTL design and supporting
- Track metrics during IP development, include development plan
milestones, code and functional coverage, defect tickets, and
tracing of requirements versusdesign specification.
- Collaborate with cross-functional teams to provide expert
support to subsystem, SoC, validation, and applications engineering
teams during product development.
- Proving design meets all requirements and ensuring zero defects
escape to silicon.
- Meeting committed schedules without compromising quality
- Definition reviews with architecture teams and designers
- Planning with verification team, architecture team, and project
- Integration of digital IP, working with local and global SoC
front-end design teams
- Support for local customers on IP, subsystem and SoC
verification teams, emulation and silicon validation teams
- Support for applications engineers and end-customers to
replicate and identify root cause field failures, and identify
- Collaborate with local and global verification and tools
development teams in developing improved methods of
- 8-10 years experience in IP or SoC design
- Knowledge of SoC architecture required
- Expert knowledge of Verilog required
- Experience with design quality checks, including Lint, clock
domain crossing (CDC) analysis, static timing analysis (STA)
- Expert knowledge of Arm AMBA bus protocol standards
- Knowledge of PCI Express or Ethernet strongly desired
- Knowledge of functional safety, including ISO26262 a plus
- Knowledge of CPU or cache architecture a plus
- Knowledge of C coding a plus
- Knowledge of scripting, such as Perl or Python, a plus
Keywords: NXP Semiconductors, Austin , R-10038434 RTL Design Engineer, Engineering , Austin, Texas
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