Design Verification Engineer
Posted on: November 19, 2021
Facebook Reality Labs focuses on delivering Facebook's vision
through Augmented Reality (AR). Compute power requirements of
Augmented Reality require custom silicon. Facebook Silicon team is
driving the state of the art forward with breakthrough work in
computer vision, machine learning, mixed reality, graphics,
displays, sensors, and new ways to map the human body. Our chips
will enable AR devices where our real and virtual world will mix
and match throughout the day. We believe the only way to achieve
our goals is to look at the entire stack, from transistor, through
architecture, to firmware, and algorithms.As a Design Verification
Engineer at Facebook Reality Labs, you will work with a world-class
group of researchers and engineers, and use your digital design and
verifications skills to implement the testing infrastructure to
validate new core IP implementations and contribute to development
and optimization of state of the art vision and sensing algorithms.
You will work closely with researchers, architects and designers in
creating test bench requirements and test cases for multiple state
of the art IPs.
- Work with researchers and architects defining verification
methodologies for each of the different core IP.
- Define and track detailed test plans for the different modules
and top levels.
- Implement scalable test benches including checkers, reference
models, coverage groups in System Verilog.
- Keep track of coverage metrics and bugs encountered and
- Implement self-testing directed and random tests.
- Support post silicon bringup and debug activities.
- Ability to communicate clearly.
- 2+ years of System Verilog OVM/UVM DV experience.
- Knowledge of Python, Perl, shell scripting.
- Knowledge with assertions (SVA) or others.
- Knowledge of digital ASICs design flows.
- Bachelors degree in Electrical Engineering or Computer Science
or equivalent experience.
- C, C++ coding, debugging experience.
- Experience as a digital design engineer.
- Experience with low power design.
- FPGA implementation and debug experience.
- Self-motivated and team player.
- Masters in Electrical Engineering or Computer Science.
Facebook's mission is to give people the power to build community
and bring the world closer together. Through our family of apps and
services, we're building a different kind of company that connects
billions of people around the world, gives them ways to share what
matters most to them, and helps bring people closer together.
Whether we're creating new products or helping a small business
expand its reach, people at Facebook are builders at heart. Our
global teams are constantly iterating, solving problems, and
working together to empower people around the world to build
community and connect in meaningful ways. Together, we can help
people build stronger communities - we're just getting started.
Facebook is proud to be an Equal Opportunity and Affirmative Action
employer. We do not discriminate based upon race, religion, color,
national origin, sex (including pregnancy, childbirth, or related
medical conditions), sexual orientation, gender, gender identity,
gender expression, transgender status, sexual stereotypes, age,
status as a protected veteran, status as an individual with a
disability, or other applicable legally protected characteristics.
We also consider qualified applicants with criminal histories,
consistent with applicable federal, state and local law.Facebook is
committed to providing reasonable accommodations for candidates
with disabilities in our recruiting process. If you need any
assistance or accommodations due to a disability, please let us
know at email@example.com Jobble
Keywords: Meta, Austin , Design Verification Engineer, Engineering , Austin, Texas
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