Validation Engineer
Company: Cadence Design Systems
Location: Austin
Posted on: February 22, 2021
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Job Description:
As a Lead Verification Engineer for Memory Controller
development team you will lead the verification effort and
contribute to the functional verification of the Cadence's Memory
Controller IP. This person will work with the existing functional
verification environment to add new features into the verification
environment, ensuring various customer configurations are clean as
part of verification regressions, supporting customers in case of
any issues with using the verification environment, and functional
and code coverage. Additionally, this person will be responsible
for ensuring that the design is in line with the technical and
quality requirements set for the team - particularly with respect
to our quality Metrics.The position is based in AustinPosition
Requirements:* BS/MS - Electrical / Computer Engineering* At least
3 years of of relevant experience including design verification
experience.* Strong background on functional verification
fundamentals, environment planning, test plan generation,
environment development is a must.* System Verilog experience and
experience with UVM based functional verification environment
development is required.* AXI 3/4/5 experience is highly desirable*
Memory controller verification experience is desirable.
Keywords: Cadence Design Systems, Austin , Validation Engineer, Engineering , Austin, Texas
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