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Design Verification Engineer

Company: TeamUP Staffing
Location: Austin
Posted on: August 3, 2020

Job Description:

As a Verification Engineer you will work closely with digitalanalog designers, participating in all aspects of verification for complete mixed-signal IC developments. The position involves verification of complex systems both at IP and SOC level as well as development of verification methodology for these complex mixed-signal systems. Responsibilities Functional verification planning and test-plan development Testbench development using UVMSystem Verilog for mixed-signal ASICs Triage and debug of design failures, coverage development and closure Generating models for functional verification, both digital and mixed signal (AMS) Stimulus generation including directed and constraint random test generation Regression debug support and infrastructure development Required Skills and Qualifications BS or MS in Electrical Engineering or Computer Engineering with 7+ years of verification experience (Mixed signal products is a plus) Strong background with SystemVerilog and methodologies like UVM, OVM, AVM or Vera Experience working with industry standard design verification EDA tools like VCS, Xcelium etc. Preferred Skills and Qualifications Experience working with object oriented programming environment Scripting languages like Perl or Python Ability to work closely with digitalanalog designers to support both pre and post silicon verification efforts Knowledge of System Verilog Assertions Experience with signal processing Contract Renewal Likely Schedule Monday to Friday Austin, TXSDL2017

Keywords: TeamUP Staffing, Austin , Design Verification Engineer, Engineering , Austin, Texas

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