Senior Dynamic Memory Controller RTL Engineer

Company: Samsung Electronics Per--
Location: Austin
Posted on: January 26, 2023

Job Description:

Position SummarySamsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology - demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional hardware and software engineers join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. Our rapidly growing System IP team develops proprietary coherent interconnect and memory controller deployed in many high volume products. A wealth of opportunities for well qualified candidates.Role and ResponsibilitiesJob DescriptionAs a senior RTL design engineer, you will work as part of a memory controller IP design team. You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller. Solid engineer foundation and RTL design experience is desired for success.Key responsibilities include:

• Produce quality RTL on schedule meeting PPA goals
• Responsible for key blocks within the Memory Controller
• Engage with others for PPA optimization
• Partner with the physical design and CAD team to resolve implementation level details
• Work closely with design verification to test plan and otherwise ensure proper functionality
• Deliver quality micro-architectural level documentationMinimum requirements:
  • BSEE, Computer Engineer or comparable and - 7+ years of experience
  • Experience owning and driving the RTL design of various sub-blocks of the memory controller for the high performance digital designs
  • Demonstrated experience of successful Architectural through RTL design experience on high performance and high efficiency digital designs
  • Detailed knowledge of memory subsystem design
  • Detailed knowledge of existing and emerging JEDEC memory standardsSkills and QualificationsPreferred candidate will possess the following:
    • Energetic, curiosity, and passion in logic design
    • Good written and verbal communication skills
    • Efficient digital design techniques
    • Knowledge of interconnect and bus protocols with Arm CHI/ACE interconnect experience preferred
    • Knowledge of cache subsystem design and optimization#SARC#ACL*This position requires the ability to access information subject to U.S. export control restrictions. - Applicants must have the ability to access export controlled information or be eligible to receive a government authorization to access export-controlled information* Please visit to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click .* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and -provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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